1. Field of the Invention
The present invention relates to silicon carbide semiconductor devices, and particularly to a silicon carbide semiconductor device including a silicon carbide substrate having a trench.
2. Description of the Background Art
The breakdown phenomenon in a gate insulating film is considered to be a main factor likely to cause a breakdown in a silicon carbide semiconductor device having a trench gate insulating film. As disclosed in Japanese Patent Laying-Open No. 2009-117593, for example, breakdown of a gate insulating film in a corner portion of a trench due to an electric field is recognized as a problem for a trench type MOSFET (Metal Oxide Semiconductor Field Effect Transistor) made of silicon carbide.
According to the technique described in the above publication, a p+ type deep layer deeper than the trench is provided in order to relax the electric field. For this purpose, a trench for providing the p+ type deep layer is formed, followed by epitaxial growth to fill this trench. In another technique according to Japanese Patent Laying-Open No. 2008-270681, for example, a p+ region is provided at the bottom of a trench by ion implantation.
According to the technique described in Japanese Patent Laying-Open No. 2009-117593, the step of forming the trench for the p+ type deep layer and the step of filling this trench are required. In other words, burdensome steps of fine processing and epitaxial growth are required.
According to the technique described in Japanese Patent Laying-Open No. 2008-270681, the ion implantation for forming the p+ region needs to be selectively performed into the bottom of the trench. This p+ region may become connected to a p region forming a channel in the trench due to manufacturing variations. In this case, a channel structure is substantially altered, causing a major disturbance in characteristics of a semiconductor device. This problem will become more pronounced as the size of the trench is further reduced.